计算机体系结构

课程组成 (bk)

• Lecture

  内容

  • Fundamentals: Chapter 1

  • Memory: Chapter 2

  • Instruction-Level Parallelism: Chapter 3

  • Data-Level Parallelism: Chapter 4

  • Thread-Level Parallelism: Chapter 5

• Lab or Research 至多2人组队，实验报告要单独写

  如果选择Lab

  共计6个 lab

  Lab 01(6%): Implement a 5-stage pipelined CPU with forwarding and predicted-not-taken to support RV32I instructions

  Lab 02(4%): Implement handling of interrupt and exception on the pipelined CPU from Lab 01

  Lab 03(3%): Implement a two-way set associative cache through simulation

  Lab 04(4%): Incorporate the two-way associative cache from Lab 03 to the pipelined CPU from Lab 02

  Lab 05(7%):Extend the pipelined CPU from Lab 02 to support multi-cycle operations, out-of-order execution, and hazard detection

  Lab 06(8%): Extend the pipelined CPU from Lab 05 to support dynamic scheduling such as Scoreboarding or Tomasulo

  好像PPT上说可以帮老师验收来得加分？

  如果选择Research

  类似于普物实验的科创项目，一学期用来做一个自定的Research，详细要求见官方文档

• Assignment & Quiz & Exam

  小测至少一次，上不封顶，没有半期。

  期末 40%